Built-In Self-Test ("BIST") is an increasingly popular means of testing large scale digital integrated circuits ("ICs") for circuit faults. A test pattern is generated on the IC to be tested; and, output data obtained by subjecting the IC to the test pattern is evaluated on the IC itself. The output data evaluation generally consists of (i) data compaction, whereby the output sequences produced by the circuit under test ("CUT") are compacted into a single signature of a few bits, and (ii) comparison of the signature with a predetermined fault-free signature to determine whether the CUT is good. However, due to the information loss through data compaction, some error responses may be mapped to the fault-free signature, thus causing some faulty circuits to escape detection. This problem is called aliasing. Usually, fault coverage before compaction can be detected by fault simulation. But, fault coverage after data compaction can usually only be estimated since exact fault simulation is not computationally feasible for large circuits. Although many probabilistic techniques have been developed, they can not be used with confidence for a specific CUT because of statistical uncertainties.
At least two kinds of signature analysis have been proposed: single signature ("SS") analysis and multiple signature ("MS") analysis (see: Bardell, P. H., McAnney, W. H. and Savir, J., "Built-In Test for VLSI: Pseudorandom Techniques", John Wiley & Sons, Inc., 1987). In the SS scheme, only a single final signature is checked at the end of a test session. In the MS scheme, however, in addition to the final signature, some intermediate signatures are checked as well. The MS scheme is known to significantly reduce aliasing. Recently, it has been shown that, besides reducing aliasing, checking multiple signatures has many other advantages over the SS scheme. For example, by checking multiple signatures, exact fault coverage after data compaction can be easily computed for large CUTs by fault simulation. Average test time can be greatly reduced by checking multiple signatures since a faulty CUT's testing session can be terminated as soon as any incorrect intermediate signature is detected. Fault diagnosability also improves with multiple signatures.
A major problem with MS schemes is that they require complex implementation and large associated hardware overhead. In "A Multiple Signature Scheme for BIST", Proc. Cdn. Conf. on VLSI 1991, the present inventors proposed a multiple signature compaction scheme for BIST. By sharing some of the circuitry required by standard single signature BIST schemes, the scheme achieves very small aliasing at the expense of small silicon area. Unfortunately, the scheme's silicon area requirements increase with test length. This makes the scheme less attractive as CUTs get larger and require long test sets. The present invention provides a new output data compaction scheme for BIST which is simple to implement and requires little hardware overhead, even compared with SS schemes, and yet has all the advantages of conventional MS schemes.